This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-195899, filed Jun. 29, 2000, the entire contents of which are incorporated herein by reference.
The present invention relates to the construction of a bonding pad portion of a semiconductor device, particularly, to the construction of a bonding pad portion of a semiconductor device constructed to permit the current density to be decreased in the metal portion so as to avoid the open circuit caused by the electromigration when an electric current flows from the bonding region to the metal wiring through a via metal.
The conventional bonding pad portion of a semiconductor device includes the type that an electric current flows from the bonding pad region into the underlying metal wiring through a via. FIG. 1 schematically shows the bonding pad portion of a semiconductor device 7.
The semiconductor device 7 shown in FIG. 1 comprises a bonding pad portion 1, a bonding wire 2, a lead frame 3, an external pin 4, an inner circuit 5, and a semiconductor chip 6. The inner circuit 5 is connected to the bonding pad portion 1 through a metal wiring (not shown).
As described above, the input-output signal relative to the inner circuit 5 of the semiconductor chip 6 and the power supply are connected in general to the external pin 4 through the bonding pad portion 1 arranged in the outer circumferential portion of the semiconductor chip 6.
The bonding pad portion in the conventional semiconductor device will now be described in detail with reference to FIGS. 2A and 2B. FIG. 2A is a plan view showing a first conventional example of the bonding pad portion, and FIG. 2B is a cross sectional view along the line IIBxe2x80x94IIB shown in FIG. 2A.
The first conventional example of the bonding pad portion shown in FIGS. 2A and 2B comprises a passivation film 50 covering the surface of the semiconductor chip, a pad open portion 10 formed in the passivation film 50, a bonding region 20a forming a connecting portion to the bonding wire 2, and an extension region 20b extended to the outside of the pad open portion 10. The bonding pad region 20a and the extension region 20b collectively form the bonding pad portion.
The extension region 20b plays the role of assuring the alignment margin when the pad open portion 10 is formed to conform with the bonding pad portion.
A metal wiring 20d having a width w and extending toward the inner region of the chip is connected integral to the bonding pad portion. The bonding pad portion to which the bonding wire 2 is connected forms a part of the metal wiring connected to the inner circuit of the semiconductor chip. In general, the bonding pad portion is also formed by using a metal wiring layer.
However, in the bonding pad portion shown in FIGS. 2A and 2B, all the input output current and the power supply current in the inner circuit of the semiconductor chip flows through the metal wiring 20d having the width w. Therefore, if the current density determined by the thickness t of the metal wiring and the width w of the wiring exceeds a predetermined critical value, an open failure is brought about by electromigration.
In order to avoid the open failure caused by the electromigration, it is necessary to lower the current density by increasing the wiring width w or the thickness t. On the other hand, if the wiring width w exceeds the width of the pad metal, the pitch between the adjacent bonding pad portions is increased so as to give rise to the problem that the number of pins per semiconductor chip is decreased.
A second conventional example of the bonding pad portion of the semiconductor device will now be described with reference to FIGS. 3A and 3B. FIG. 3A is a plan view showing the second conventional example of the bonding pad portion, and FIG. 3B is a cross sectional view along the line IIIBxe2x80x94IIIB shown in FIG. 3A.
In FIGS. 3A and 3B, the members of the semiconductor device equal to those shown in FIGS. 2A and 2B are denoted by the same reference numerals so as to avoid the overlapping description. In the first conventional example shown in FIGS. 2A and 2B, the bonding pad portion is connected integral to the metal wiring 20d to form a current path leading to the inner circuit of the semiconductor chip.
In the second conventional example shown in FIGS. 3A and 3B, however, the other metal wiring 20d is interposed between the bonding pad portion and the inner circuit of the semiconductor chip in an upper metal wiring layer equal to the bonding pad portion. In this case, the current of the bonding wire 2 flows from an upper via metal connection region 20c formed in a side of the extension region 20b of the bonding pad portion into an underlying via metal connection region 30c through a plurality of via metals 25 so as to be introduced into the inner circuit by an underlying metal wiring 30d. 
Incidentally, an interlayer insulating film 70 plays the role of isolating the underlying metal wiring 30d from the underlying structure.
In the bonding pad portion shown in FIGS. 3A and 3B, the input-output signal current and the power supply current of the inner circuit of the semiconductor chip flows into the underlying metal wiring 30d through the plural via metals 25. It should be noted that current concentration tends to take place easily in the via metal 25. Also, since the underlying metal wiring has in general a thickness t smaller than that of the upper metal wiring, an open failure caused by electromigration tends to take place more easily in the bonding pad portion of the second conventional example than in the first conventional example.
A third conventional example of the bonding pad portion of the semiconductor device will now be described with reference to FIG. 4. In the third conventional example shown in FIG. 4, the upper via metal connecting region 20c formed in a side of the extension region 20b of the bonding region 20a in addition to the upper metal wiring 20d is connected to the underlying via metal connecting region 30c through a plurality of via metals 25 in order to avoid the open failure caused by the electromigration in the bonding pad portion for the first conventional example, and a current path leading to the inner circuit is formed by the upper and underlying metal wirings 20d and 30d. 
A fourth conventional example of the bonding pad portion of the semiconductor device will now be described with reference to FIG. 5. In the fourth conventional example shown in FIG. 5, the upper via metal connecting region 20c formed in a side of the extension region 20b of the bonding region 20a is connected to underlying via metal connecting regions 30c, 40c formed below the upper metal wiring layer 20d through a plurality of vias 25, 35 in order to avoid the open failure caused by the electromigration in the bonding pad portion, which is inherent in the second conventional example described above with reference to FIGS. 3A and 3B, and a current path leading to the inner circuit is formed by the underlying metal wirings 30d, 40d connected to the underlying via metal connecting regions 30c, 40c, respectively.
If the metal wiring forming a current path leading to the inner circuit is of a two-layer structure as in the third and fourth conventional examples, the current density is markedly lowered, with the result that it is possible to avoid the electromigration in the metal wiring. However, the entire current is concentrated on the Xxe2x80x94X cross section of the upper via metal connecting region in each of FIGS. 4 and 5 so as to increase the current density, with the result that an open failure tends to be caused by the electromigration.
Also, in FIG. 5, the entire current is concentrated on the upper plural vias 25, with the result that an open failure also tends to be caused by the electromigration. Incidentally, an interlayer insulating film 80 shown in FIG. 5 plays the role of isolating the underlying metal wiring 40d from the lower structure.
As described above, the bonding pad portion in the conventional semiconductor device was defective in that the current density is rendered high in, for example, the metal wiring serving to connect the bonding pad portion to the inner circuit, and in the plural via metals serving to connect the bonding pad portion to the underlying metal wiring, with the result that an open failure tends to be caused by the electromigration.
The semiconductor device of the present invention comprises a branched path consisting of an underlying metal wiring layer of at least one layer arranged in the periphery of the bonding pad portion consisting of an upper metal wiring layer.
To be more specific, the input-output signal current and the power supply current flowing though the bonding wire into the inner circuit of the semiconductor chip is branched from the upper via metal connecting region formed in an extension region of the bonding pad portion into an underlying via metal connecting region consisting of at least one layer through a plurality of via metals.
By forming a current path leading to the inner circuit, said current path consisting of a multi-layered metal wiring, by using the underlying metal wiring connected to each of the via metal connecting regions, it is possible to moderate the current concentration occurring in the past in the metal wiring for connecting the bonding pad portion to the inner circuit so as to avoid an open failure caused by the electromigration.
According to a first aspect of the present invention, there is provided a semiconductor device, comprising a plurality of metal wiring layers laminated one upon the other on a semiconductor chip with an interlayer insulating film interposed therebetween; a bonding pad portion formed on an upper metal wiring layer in said plural metal wiring layers; a passivation film formed to cover the bonding pad portion; a pad open portion formed in the passivation film; and an underlying pad structure in at least one layer of the underlying metal wiring layer included in the plural metal wiring layers; wherein the bonding pad portion includes a bonding region covering the bottom surface of the pad open portion, an extension region extending from the bottom surface of the pad open portion to the outside of the bonding wire connecting portion, and via metal connecting region formed on the outside of the extension region along at least one side of the extension region; the lower bonding pad structure includes an underlying via metal connecting region formed to surround the bonding region; and the upper via metal connecting region is connected to the underlying via metal connecting region through a plurality of via metals formed through the interlayer insulating film positioned adjacent to the lower portion of the upper metal wiring layer.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.